1. Field of Invention
The present invention relates generally to interrupt handling. More particularly, the present invention relates to selecting processors in a multiprocessor system to run interrupt handlers.
2. Description of the Related Art
Peripheral components and peripheral interfaces use hardware interrupts to notify processors that attention is being requested. When a processor detects an interrupt, the processor saves information to allow the processor to later return to the current processing, and executes an interrupt handler or interrupt service routine. The interrupt handler or interrupt service routine provides instructions for processing the interrupt. To allow efficient handling of multiple peripherals, systems often use an interrupt controller to act as an intermediary between processors and peripherals. The interrupt controller prioritizes the various interrupts and sends them to particular processors. In multiprocessor systems, the interrupt controller not only prioritizes the interrupts, but can distribute them as well.
One conventional scheme for selecting processors is round-robin. A first identified interrupt is handled by a first processor, a second identified interrupt is handled by a second processor, a third identified interrupt is handled by the first processor, etc. Other conventional techniques bind peripheral components and peripheral interfaces to particular processors. In one example, interrupts arising from a communication adapter are handled by first processor, interrupts arising from a storage card are handled by a second processor, etc. Conventional techniques, however, fail to consider the characteristics associated with the interrupts. For example, a multiprocessor system may be handling two text message sessions and two processor intensive video sessions. Using a round-robin or a static binding methodology, the same processor may be assigned to handle both the processor intensive video sessions. The other processors may be handling the less processor intensive text message sessions. In this example, response time of the multiprocessor system may be slow even though ample processing resources are available.
Consequently, it is desirable to provide improved techniques for distributing interrupts to a plurality of processors for interrupt handling in the multiprocessor system.